VLSI and Analog Circuit Testing

Testing the correctness and reliability of modern integrated circuits is far harder than designing them: a chip containing billions of transistors must be verified against an enormous range of possible manufacturing defects, often with only limited access to internal nodes and strict constraints on time, power, and data volume. Researchers develop methods such as scan-based testing, built-in self-test schemes, and test data compression to make exhaustive fault detection practical without overwhelming the interface between a chip and external test equipment—challenges that grow sharper as designs incorporate reusable embedded cores whose internal logic is largely opaque to the system integrator. Analog and mixed-signal circuits add a further layer of difficulty, since their faults manifest as continuous parametric deviations rather than discrete logic errors, demanding specialized diagnosis techniques that sit at the intersection of signal processing and circuit theory. Active open questions include how to maintain adequate fault coverage while drastically reducing the power consumed during test, and how to construct scalable test access architectures for systems-on-chip that aggregate dozens of heterogeneous cores under a single, coordinated test regime.

Works

57,723

Total citations

456,816

Keywords

Test Data CompressionEmbedded CoresScan TestingAnalog Circuit Fault DiagnosisBIST SchemeTest Access Architecture